The present invention relates to computer system clocks and, more particularly, relates to a fractional-N phase locked loop (PLL) computer clock driven by a spread spectrum clock (SSC) gating signal to reduce electromagnetic interference.
Computer clocks are a known source of electromagnetic interference (EMI), which is a disturbance that adversely affects electrical circuits. This disruption can limit and degrade the performance of these circuits. Spread spectrum clocking is a technique in which a particular clock frequency is spread in the frequency domain to correspondingly spread out the EMI over a wider bandwidth to reduce the concentration of the interference. Systems for reducing EMI using various SSC approaches have been practiced for generations. Historically, these approaches required multiple high frequency clock generators operating at the desired range of output frequencies, which are combined in some fashion to create the SSC clock signal.
Phase Locked Loop (PLL) frequency multiplier chips have been developed for generating high frequency computer clocks from lower frequency reference clocks. This approach utilizes a crystal oscillator to generate a relatively slow base frequency known as the reference clock. The reference clock is then fed into the PLL, which multiplies the frequency to generate an output clock that is anywhere from one to one hundred times the base reference clock. The PLL multiplication rate may typically be varied using a feedback control signal, for example over a range of ±1% around the base multiplication rate, to provide an SSC characteristic to the output clock. The spread spectrum output clock produced by the PLL is then utilized as the final SSC output clock for the design. With this approach, varying the PLL multiplication rate to spread the output clock spectrum typically requires multiple feedback clocks operating at desired range of output frequencies. The various feedback clocks are combined in some manner to create the feedback signal to drive the PLL multiplication rate to produce the variable frequency SSC output clock. Generating and combining multiple high frequency feedback clocks to create the SSC gating signal requires complex circuitry and control techniques that become impractical as the desired output frequency increases.